A liquid crystal display device may include a buffer having a low output impedance and outputting an amplified (in broad sense of the term) signal. A member so called buffer can be a level-shifter for performing a translation of a source voltage or an amplifier for receiving an input signal and outputting an amplified signal with unity gain. In a case where the buffer includes CMOS transistors, it is required that p-channel transistors and n-channel transistors be formed in respective processes. The buffer may include transistors all of which have only a single type of channel polarity, such as n-channel, so that the forming steps can be simplified (see, for example, Patent Literature 1).
FIGS. 18 and 19 each show an example of a configuration of a buffer which includes n-channel transistors but no p-channel transistors. The buffer has input terminals In and Inb for a set of inputs with opposite phases.
As shown in FIG. 18, transistors 201 through 203 have respective sources connected to VSS. In a case where the input terminal In receives VDD and the input terminal Inb receives VSS, the transistors 201 through 203, having respective gates connected to the input terminal In, are turned ON, while a transistor 204, having a gate connected to the input terminal Inb and a drain connected to VDD, is turned OFF. Thus, an electric potential at a point 210, at which the transistors 201 and 204 are connected to each other, is caused to be VSS. The point 210 is connected to a gate of a transistor 205 and that of a transistor 206, the transistor 205 connected to a VDD side of the transistor 202 in series and the transistor 206 connected a VDD side of the transistor 203 in series. The transistors 205 and 206 have respective drains connected to VDD.
Thus, the transistors 205 and 206 are turned OFF.
Since the transistor 206 is turned OFF and the transistor 203 is turned ON, VSS is outputted to an output terminal OUT.
As shown in FIG. 19, in a case where the input terminal In receives VSS and the input terminal Inb receives VDD, the transistors 201 through 203 are turned OFF, while the transistor 204 is turned ON. Thus, an electric potential at the point 210 is increased to be “VDD−threshold voltage Vth of the transistor 204”. As the electric potential at the point 210 is increased, the transistor 205 becomes turned ON, thereby causing an increase in a drain current of the transistor 205. Then, the transistor 204 is turned OFF at a time when the electric potential of the point 210 reaches “VDD−threshold voltage Vth of the transistor 204”.
A bootstrap capacitor 101 is connected between the gate and the source of the transistor 205. In a case where an electric potential at a point 211, which is connected to the source of the transistor 205, is increased, the bootstrap capacitor 101 causes the electric potential at the point 210 to be instantaneously increased. In consideration, by designing such that the electric potential at the point 210 is instantaneously increased to be “VDD+threshold voltage Vth of the transistor 205” or higher, it is possible to cause the electric potential at the point 211 to be increased to VDD without being decreased in voltage by the degree of the threshold voltage Vth. A capacitor 100 is connected between the drain and the gate of the transistor 202.
Since the electric potential at the point 210 is inputted also to the gate of the transistor 206, an output to the output terminal OUT is VDD which is not decreased in voltage by the threshold voltage Vth.
With reference to FIGS. 20 and 21, the following describes another example of a configuration of the buffer which includes n-channel transistors but no p-channel transistor. The buffer is a single-phase input buffer including only an input terminal In. According to a configuration shown in FIGS. 20 and 21, an input terminal Inb as shown in FIGS. 18 and 19 is removed, and a transistor 204 has a gate and a drain connected to each other.
As shown in FIG. 20, in a case where the input terminal In receives VDD, transistors 201 through 203 are turned ON. This causes an electric potential at a point 210 to be VSS, such that a drain-to-source voltage, i.e., a gate-to-source voltage, of the transistor 204 is caused to be “VDD−VSS”. Thus, the transistor 204 is turned ON, and by this, a pass-through current passing through the transistor 204 is generated. According to the configuration shown in FIG. 20, a size ratio between the transistors 204 and 201 is set such that the electric potential at the point 210 will be closer to VSS. The electric potential at the point 210 is inputted to respective gates of the transistors 205 and 206, such that both the transistors 205 and 206 are turned OFF. Since the transistor 203 is turned ON and the transistor 206 is turned OFF, VSS is outputted via an output terminal OUT.
As shown in FIG. 21, in a case where the input terminal In receives VSS, the transistors 201 through 203 are turned OFF, while the transistor 204 is turned ON as in the case with FIG. 20. This causes the electric potential at the point 210 to be increased from VSS toward “VDD−threshold voltage Vth of the transistor 204”. As the electric potential at the point 210 is increased, the transistor 205 becomes turned ON, thereby causing an increase in a drain current of the transistor 205. Then, the transistor 205 is turned OFF at a time when the electric potential at the point 210 reaches “VDD−threshold voltage Vth of the transistor 204”.
In the above condition, in a case where the electric potential at the point 211 is increased, the bootstrap capacitor 101 causes the electric potential at the point 210 to be instantaneously increased. In consideration, by designing such that the electric potential at the point 210 is instantaneously increased to “VDD+threshold voltage Vth of the transistor 205” or higher, it is possible to cause the electric potential at the point 211 to be increased to VDD without being decreased in voltage by the degree of the threshold voltage Vth.
The electric potential at the point 210 is inputted also to the gate of the transistor 206. Consequently, an output to the output terminal OUT is VDD which is not decreased in voltage by the threshold voltage Vth.
In the case with the single-phase input buffer as shown in FIGS. 20 and 21, the pass-through current is generated. Thus, it is required that a consumption current be reduced. In practice, however, the pass-through current is prevented by designing a transistor 204 having a narrower channel width W or replacing the transistor 204 with a resistor having a high resistance value.
FIG. 22 shows a configuration in which the transistor 204 is replaced by a resistor T having a high resistance value. In the configuration, the pass-through current is reduced by the resistor T. According to the configuration, (i) in a case where the input terminal In receives VDD, the output terminal OUT has the same electric potential as in the case with FIG. 20, and (ii) in a case where the input terminal In receives VSS, the output terminal OUT has the same electric potential as in the case with FIG. 21.